The present invention relates to a semiconductor memory formed on a semiconductor substrate, and more particularly to a semiconductor memory IC having a serially addressing scheme for serially reading a plurality of bit locations without address information from the outside.
Many kinds of memories have been developed and used widely in accordance with purposes and applications. Of those, a memory having a large capacity is used in a system handling large amount of data such as those for voices or images. The memory of this kind is not required to operate at a very high speed, but to be easy to use at low cost. Therefore, a memory of serially addressing type has been proposed, and devices have been made to minimize the number of external pins so as to reduce the cost. As one of approaches to achieve the above, a reduction in the number of address terminals has been proposed and practised. Since such a memory having a large memory capacity has a wide address space which requires a large address bit length. This makes it necessary to use a great number of address terminals if the conventional address access system is adopted. For example, eighteen address terminals are required in case a memory composed of 320 word lines in rows and 700 bit lines (or bit line pairs) in columns to have a capacity of 224 kbits is to be produced. On the other hand, it is a current practice to access the voice or image data not at random but sequentially in a fixed order of columns so that the column addresses are repeatedly renewed. As a result, the column address terminals can be dispensed with if a counter or a shift register is provided inside of a memory and is incremented or decremented to generate a column address. Thus, a plurality bits of data read on bit lines in columns are sequentially addressed one by one by incrementing or decrementing contents of the counter or shift register.
Since the memory of this kind need not receive any column address from the outside, it is advantageous in that it can be fabricated at a low cost and used easily. However, the memory is disadvantageous in that which column is being accessed, i.e., which bit line the data being read or written cannot be known from the outside of the memory. In the memory of this kind, generally speaking, after all the data set in an output data register have been read out, the data held in this register have to be written again in the original locations. This operation is generally performed independently of a refreshing operation although it can be conducted together with the latter operation. Moreover, the writing operation is required for maintaining the memory data. Since, however, the user of this memory cannot know from the outside when the read of the data (of 700 bits, for example) of one word is to from the outside to a row decoder for performing a word selecting signal is counted by a counter, which is prepared outside of the memory, to locate the position of the bit being accessed, by which the aforementioned rewrite timing is checked. This raises a serious defect that the number of parts to be added to the outside of the memory is increased to complicate the system design and to necessarily raise the cost. Even if the check is conducted outside, moreover, the timing detected at the outside and the actual timing in the memory are not necessarily coincident, and there is possibility of a discrepancy in the timing due to characteristic dispersions depending upon the different lengths of the signal lines and the fabricating conditions of the memory. This problem is predicted to become the more prominent especially as the number of cells per one word line (or one bit line) becomes the greater.